Integrated silicon based photonics currently include dielectric waveguides in combination with optically coupled silicon waveguides in a single device. The dielectric waveguide has a waveguide core made of amorphous dielectric material. The silicon waveguide carries light in a waveguide core made of single crystal silicon.
The dielectric waveguide, when coupled to an optical fiber, has a low loss, exhibits lower propagation loss, and has a wide spectral bandwidth. Silicon waveguides can be used in the realization of active optical devices such as modulators, detectors, and others.
International patent application WO2014/047443 discloses wafer scale integration of ultra-low-loss dielectric waveguides with silicon and/or compound semiconductor waveguides on a common substrate. The method disclosed is based on the fact that the silicon and/or compound semiconductor waveguides and other active optical devices are formed after the dielectric waveguide has been formed and annealed at a high temperature (typically above 900° C.). To enable this, a bonding step is introduced that defines the cladding layer of the dielectric waveguide. Although the method allows the combination of two disparate waveguide technologies by a bonding step, it introduces a bonding interface in the cladding layer between the dielectric waveguide core and the first region of the semiconductor layer that is optically coupled to the dielectric waveguide core.
This bonding has a detrimental effect on the optical coupling between the dielectric waveguide core and the first region of the semiconductor layer through the inter-waveguide cladding layer. This detrimental effect is caused by a limited control of the thickness of the inter-waveguide cladding layer between the dielectric waveguide core and the first region of the semiconductor layer. First, the cladding deposition, usually performed by chemical vapor deposition (CVD), has a finite controllability. Second, the required polishing step of this nascent cladding layer prior to bonding is not well-controlled. Chemical Mechanical Polishing (CMP) is used to polish the nascent cladding layer. This technique is known in the art to suffer from oxide loss, dishing, and erosion, and these effects will cause local and global thickness variation in the thickness of the inter-waveguide cladding layer after the bonding step. The thickness is nevertheless a critical design parameter for the optical coupling between the dielectric waveguide core and the first region of the semiconductor layer. Especially on wafer scale, these thickness variations will be more pronounced and cause dispersion in optical coupling observed in multiple identical optically integrated devices on a single wafer.
International patent application WO2014/047443 further discloses that the total thickness after bonding of the inter-waveguide cladding is equal to the combined thickness of the nascent cladding layer and thickness of the thermally grown oxide.
International patent application WO2014/047443 further discloses that the thickness of the nascent cladding layer can be controlled with extremely high precision, and that this control of thickness is used to enable high precision of the final total thickness by controlling the thermal oxidation and tailoring the thickness of the nascent cladding layer to the desired total thickness minus a measured value of the thickness of the thermally grown oxide. This method only allows compensation for a measured (average) value of the thickness variation and does not take into account the local thickness variations introduced by the CMP. Because the thermally grown oxide is conformal and will exhibit the same thickness over the whole surface, the local variation will remain present in the final total thickness.
There is a need to improve further the uniformity of the optical coupling through the inter-waveguide cladding.